Product Summary
The CY2309ZC-1H is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309ZC-1H. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309ZC-1H has two banks of four outputs each, which can be controlled by the Select inputs as shown in the “Select Input Decoding” table on page 2.
Parametrics
CY2309ZC-1H absolute maximum ratings: (1)Supply Voltage to Ground Potential: -0.5V to +7.0V; (2)DC Input Voltage (Except REF): -0.5V to VDD + 0.5V; (3)DC Input Voltage REF: -0.5V to 7V; (4)Storage Temperature: -65℃ to +150℃; (5)Junction Temperature: 150℃; (6)Static Discharge Voltage (per MIL-STD-883, Method 3015): > 2,000V.
Features
CY2309ZC-1H features: (1)10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies; (2)Zero input-output propagation delay; (3)Multiple low-skew outputs, Output-output skew less than 250 ps; Device-device skew less than 700 ps; One input drives five outputs (CY2305); One input drives nine outputs, grouped as 4 + 4 + 1(CY2309); (4)Less than 200 ps cycle-cycle jitter, compatible with Pentium.-based systems; (5)Test Mode to bypass phase-locked loop (PLL) (CY2309 only [see Select Input Decoding on page 2]); (6)Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305); (7)3.3V operation; (8)Industrial temperature available.
Diagrams
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![]() Phase Locked Loops (PLL) 3.3VZDB COM |
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![]() CY2300 |
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![]() CY2300SXC |
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![]() Phase Locked Loops (PLL) 3.3VZDB COM |
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![]() CY2300SXCT |
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![]() CY2302 |
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![]() CY23020-1 |
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![]() CY23020LFI-3 |
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![]() Phase Locked Loops (PLL) 400MHz IND Zero Delay Buffer |
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![]() Negotiable |
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