Product Summary
The CDC351DBR is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The CDC351DBR operates at nominal 3.3-V VCC. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND. The CDC351DBR is characterized for operation from 0℃ to 70℃.
Parametrics
CDC351DBR absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 4.6 V; (2)Input voltage range, VI: -0.5 V to 7 V; (3)Voltage range applied to any output in the high state or power-off state, VO: -0.5 V to 3.6 V; (4)Current into any output in the low state, IO: 64 mA; (5)Input clamp current, IIK (VI < 0): -18 mA; (6)Output clamp current, IOK (VI < 0): -50 mA; (7)Maximum power dissipation at TA = 55℃ (in still air): DB package: 0.65 W; DW package: 1.7 W; (8)Storage temperature range, Tstg: -65 to 150℃.
Features
CDC351DBR features: (1)Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications; (2)Operates at 3.3-V VCCLVTTL-Compatible Inputs and Outputs; (3)Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC); (4)Distributes One Clock Input to Ten Outputs; (5)Distributed VCC and Ground Pins Reduce Switching Noise; (6)High-Drive Outputs (–32-mA IOH, 32-mA IOL); (7)State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation; (8)Package Options Include Plastic Small-Outline (DW) and Shrink; Small-Outline (DB) Packages.
Diagrams
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![]() CDC351DBR |
![]() Texas Instruments |
![]() Clock Drivers & Distribution 1-Line to 10-Line Clock Driver |
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![]() CDC351DBRG4 |
![]() Texas Instruments |
![]() Clock Drivers & Distribution 1-Line to 10-Line Clock Driver |
![]() Data Sheet |
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