EPM7256AEFC256-7

Product Summary

The EPM7256AEFC256-7 is a high-density, high-performance device based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based the device operates with a 3.3-V supply voltage and provides 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. The EPM7256AEFC256-7 in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM7256AEFC256-7 absolute maximum ratings: (1)Supply voltage, VCC: -0.5 to 4.6 V; (2)DC input voltage, VI: -2.0 to 5.75 V; (3)DC output current, per pin, IOUT: -25 to 25 mA; (4)Storage temperature No bias, TSTG: -65 to 150℃; (5)Ambient temperature Under bias, TA: -65 to 135℃; (6)Junction temperature BGA, FineLine BGA, PQFP, and TQFP packages, under bias, TJ: 135℃.

Features

EPM7256AEFC256-7 features: (1)High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture; (2)3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability, MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532; EPM7128A and EPM7256A device ISP circuitry compatible with ; (3)IEEE Std. 1532; (4)Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1; (5)Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71; (6)Enhanced ISP features, Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices); ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices); Pull-up resistor on I/O pins during in-system programming; (7)Pin-compatible with the popular 5.0-V MAX 7000S devices; (8)High-density PLDs ranging from 600 to 10,000 usable gates; (9)Extended temperature range.

Diagrams