AD9865BCPZ

Product Summary

The AD9865BCPZ is a mixed-signal front end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 80 MSPS. Its flexible digital interface, power saving modes, and high Tx-to-Rx isolation make the AD9865BCPZ well suited for half- and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends that support half- or full-duplex data transfers, thus often allowing the AD9865BCPZ to replace discrete ADC and DAC solutions. Power saving modes include the ability to reduce power consumption of individual functional blocks, or to power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source. The AD9865BCPZ is suitable for Powerline networking and VDSL and HPNA.

Parametrics

AD9865BCPZ absolute maximum ratings: (1)AVDD, CLKVDD Voltage: 3.9 V maximum; (2)DVDD, DRVDD Voltage: 3.9 V maximum; (3)RX+, RX?, REFT, REFB: -0.3 V to AVDD + 0.3 V; (4)IOUTP+, IOUTP-: -1.5 V to AVDD + 0.3 V; (5)IOUTN+, IOUTN-, IOUTG+, IOUTG-: -0.3 V to +7 V; (6)OSCIN, XTAL: -0.3 V to CLVDD + 0.3 V; (7)REFIO, REFADJ: -0.3 V to AVDD + 0.3 V; (8)Digital Input and Output Voltage: -0.3 V to DRVDD + 0.3 V; (9)Digital Output Current: 5 mA maximum; (10)Operating Temperature Range (Ambient): -40℃ to +85℃; (11)Maximum Junction Temperature: 125℃; (12)Lead Temperature (Soldering, 10 s): 150℃; (13)Storage Temperature Range (Ambient): -65 to +150℃.

Features

AD9865BCPZ features: (1)Low cost 3.3 V CMOS MxFE for broadband modems; (2)10-bit D/A converter: 2×/4× interpolation filter; 200 MSPS DAC update rate; (3)Integrated 23 dBm line driver with 19.5 dB gain control; (4)10-bit, 80 MSPS A/D converter; (5)-12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz); (6)Third order, programmable low-pass filter; (7)Flexible digital data path interface: Half- and full- duplex operation; Backward-compatible with AD9975 and AD9875; (8)Various power-down/reduction modes; (9)Internal clock multiplier (PLL); (10)2 auxiliary programmable clock outputs; (11)Available in 64-lead chip scale package or bare die.

Diagrams